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Fix depth-stencil formats
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b4280a61ac
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179363a5e7
@ -94,10 +94,10 @@ namespace skyline::gpu::interconnect {
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TIC_FORMAT_CASE_INT_FLOAT(R32, R32);
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TIC_FORMAT_CASE_ST(D32, D32, Float);
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TIC_FORMAT_CASE_NORM_INT_FLOAT(R16G16, R16G16);
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TIC_FORMAT_CASE(R8G24, D24UnormS8Uint, Uint, Unorm, Unorm, Unorm);
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TIC_FORMAT_CASE(S8D24, D24UnormS8Uint, Uint, Unorm, Uint, Uint);
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TIC_FORMAT_CASE(S8D24, D24UnormS8Uint, Uint, Unorm, Unorm, Unorm);
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TIC_FORMAT_CASE(D24S8, S8UintD24Unorm, Unorm, Uint, Uint, Uint);
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TIC_FORMAT_CASE(R8G24, S8UintD24Unorm, Uint, Unorm, Unorm, Unorm);
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TIC_FORMAT_CASE(S8D24, S8UintD24Unorm, Uint, Unorm, Uint, Uint);
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TIC_FORMAT_CASE(S8D24, S8UintD24Unorm, Uint, Unorm, Unorm, Unorm);
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TIC_FORMAT_CASE(D24S8, D24UnormS8Uint, Unorm, Uint, Uint, Uint);
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TIC_FORMAT_CASE_ST(B10G11R11, B10G11R11, Float);
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TIC_FORMAT_CASE_NORM_INT(A8B8G8R8, R8G8B8A8);
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@ -231,7 +231,7 @@ namespace skyline::gpu::format {
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.g = vk::ComponentSwizzle::eR,
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.b = vk::ComponentSwizzle::eB,
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.a = vk::ComponentSwizzle::eA,
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});
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}, true);
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FORMAT(S8Uint, 32, eS8Uint, .vkAspect = {
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vka::eStencil
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}, .swizzleMapping = {
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