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Fix Depth RT layer stride

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The layer stride provided by the depth register in Maxwell3D needs to be shifted by 2, this caused the stride to be 1/4th of what it needed to be resulting in OOB access.
This commit is contained in:
PixelyIon 2023-01-30 21:07:51 +05:30 committed by Billy Laws
parent df3b961d5d
commit 3407f5a6d1
2 changed files with 7 additions and 3 deletions
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4
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/pipeline_state.cpp
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@ -87,7 +87,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
/* Depth Render Target */ /* Depth Render Target */
void DepthRenderTargetState::EngineRegisters::DirtyBind(DirtyManager &manager, dirty::Handle handle) const { void DepthRenderTargetState::EngineRegisters::DirtyBind(DirtyManager &manager, dirty::Handle handle) const {
manager.Bind(handle, ztSize, ztOffset, ztFormat, ztBlockSize, ztArrayPitch, ztSelect, ztLayer, surfaceClip); manager.Bind(handle, ztSize, ztOffset, ztFormat, ztBlockSize, ztArrayPitchLsr2, ztSelect, ztLayer, surfaceClip);
} }
DepthRenderTargetState::DepthRenderTargetState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine) : engine{manager, dirtyHandle, engine} {} DepthRenderTargetState::DepthRenderTargetState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine) : engine{manager, dirtyHandle, engine} {}
@ -121,7 +121,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
.blockDepth = engine->ztBlockSize.BlockDepth(), .blockDepth = engine->ztBlockSize.BlockDepth(),
}; };
guest.layerStride = (guest.baseArrayLayer > 1 || guest.layerCount > 1) ? engine->ztArrayPitch : 0; guest.layerStride = (guest.baseArrayLayer > 1 || guest.layerCount > 1) ? engine->ZtArrayPitch() : 0;
auto mappings{ctx.channelCtx.asCtx->gmmu.TranslateRange(engine->ztOffset, guest.GetSize())}; auto mappings{ctx.channelCtx.asCtx->gmmu.TranslateRange(engine->ztOffset, guest.GetSize())};
guest.mappings.assign(mappings.begin(), mappings.end()); guest.mappings.assign(mappings.begin(), mappings.end());

6
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/pipeline_state.h
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@ -40,12 +40,16 @@ namespace skyline::gpu::interconnect::maxwell3d {
const soc::gm20b::engine::Address &ztOffset; const soc::gm20b::engine::Address &ztOffset;
const engine::ZtFormat &ztFormat; const engine::ZtFormat &ztFormat;
const engine::ZtBlockSize &ztBlockSize; const engine::ZtBlockSize &ztBlockSize;
const u32 &ztArrayPitch; const u32 &ztArrayPitchLsr2;
const engine::ZtSelect &ztSelect; const engine::ZtSelect &ztSelect;
const engine::ZtLayer &ztLayer; const engine::ZtLayer &ztLayer;
const engine::SurfaceClip &surfaceClip; const engine::SurfaceClip &surfaceClip;
void DirtyBind(DirtyManager &manager, dirty::Handle handle) const; void DirtyBind(DirtyManager &manager, dirty::Handle handle) const;
u32 ZtArrayPitch() const {
return ztArrayPitchLsr2 << 2;
}
}; };
private: private: