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Implement linked TIC/TSC handle in Maxwell3D
Maxwell3D has a register for linking the TIC/TSC index in bindless texture handles, this is used by games to implement bindless combined texture-sampler handles.
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@ -1176,6 +1176,8 @@ namespace skyline::gpu::interconnect {
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auto &constantBuffer{pipelineStage.constantBuffers[texture.cbuf_index]};
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BindlessTextureHandle handle{constantBuffer.Read<u32>(executor, texture.cbuf_offset)};
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if (tscIndexLinked)
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handle.samplerIndex = handle.textureIndex;
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auto sampler{GetSampler(handle.samplerIndex)};
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auto textureView{GetPoolTextureView(handle.textureIndex)};
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@ -2292,6 +2294,8 @@ namespace skyline::gpu::interconnect {
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/* Samplers */
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private:
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bool tscIndexLinked{}; //!< If the TSC index in bindless texture handles is the same as the TIC index or if it's independent from the TIC index
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struct Sampler : public vk::raii::Sampler, public FenceCycleDependency {
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using vk::raii::Sampler::Sampler;
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};
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@ -2319,6 +2323,10 @@ namespace skyline::gpu::interconnect {
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samplerPool.samplerControls = nullptr;
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}
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void SetTscIndexLinked(bool isTscIndexLinked) {
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tscIndexLinked = isTscIndexLinked;
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}
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private:
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vk::Filter ConvertSamplerFilter(TextureSamplerControl::Filter filter) {
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using TscFilter = TextureSamplerControl::Filter;
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@ -129,6 +129,10 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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context.SetDepthRenderTargetArrayMode(depthTargetArrayMode);
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})
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ENGINE_CASE(linkedTscHandle, {
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context.SetTscIndexLinked(linkedTscHandle);
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});
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#define VIEWPORT_TRANSFORM_CALLBACKS(_z, index, data) \
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ENGINE_ARRAY_STRUCT_CASE(viewportTransforms, index, scaleX, { \
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context.SetViewportX(index, scaleX, registers.viewportTransforms[index].translateX); \
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@ -151,6 +151,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x48B, u32> depthTargetHeight;
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Register<0x48C, type::RenderTargetArrayMode> depthTargetArrayMode;
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Register<0x48D, bool> linkedTscHandle; //!< If enabled, the TSC index in a bindless texture handle is ignored and the TIC index is used as the TSC index, otherwise the TSC index from the bindless texture handle is used
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Register<0x4B3, u32> depthTestEnable;
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Register<0x4B9, u32> independentBlendEnable;
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Register<0x4BA, u32> depthWriteEnable;
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