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https://github.com/skyline-emu/skyline.git
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Add partial conditional rendering support
Disabled for cases where the results come from queries rn, however still functional for cases like AC which don't use it with queries.
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a2798a9184
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@ -616,6 +616,7 @@ namespace skyline::gpu::interconnect {
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slot->nodes.splice(slot->nodes.end(), slot->pendingPostRenderPassNodes);
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{
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slot->WaitReady();
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@ -62,6 +62,47 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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beginMethodTopology : type::ConvertPrimitiveTopologyToDrawTopology(*registers.primitiveTopology);
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}
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bool Maxwell3D::CheckRenderEnable() {
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if (registers.renderEnableOverride->mode == Registers::RenderEnableOverride::Mode::AlwaysRender)
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return true;
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else if (registers.renderEnableOverride->mode == Registers::RenderEnableOverride::Mode::NeverRender)
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return false;
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switch (registers.renderEnable->mode) {
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case Registers::RenderEnable::Mode::True:
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return true;
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case Registers::RenderEnable::Mode::False:
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return false;
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case Registers::RenderEnable::Mode::Conditional:
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// TODO: Use indirect draws to emulate conditional rendering with queries, for now just ignore such cases as they would decrease performance anyway by forcing a CPU sync
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if (interconnect.QueryPresentAtAddress(u64{registers.renderEnable->offset}))
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return true;
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return channelCtx.asCtx->gmmu.Read<u32>(registers.renderEnable->offset) != 0;
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case Registers::RenderEnable::Mode::RenderIfEqual:
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// TODO: See above
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if (interconnect.QueryPresentAtAddress(u64{registers.renderEnable->offset}) ||
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interconnect.QueryPresentAtAddress(u64{registers.renderEnable->offset + 16}))
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return true;
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return channelCtx.asCtx->gmmu.Read<u32>(registers.renderEnable->offset) ==
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channelCtx.asCtx->gmmu.Read<u32>(registers.renderEnable->offset + 16);
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case Registers::RenderEnable::Mode::RenderIfNotEqual:
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// TODO: See above
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if (interconnect.QueryPresentAtAddress(u64{registers.renderEnable->offset}) ||
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interconnect.QueryPresentAtAddress(u64{registers.renderEnable->offset + 16}))
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return true;
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return channelCtx.asCtx->gmmu.Read<u32>(registers.renderEnable->offset) !=
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channelCtx.asCtx->gmmu.Read<u32>(registers.renderEnable->offset + 16);
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}
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return true;
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}
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Maxwell3D::Maxwell3D(const DeviceState &state, ChannelContext &channelCtx, MacroState ¯oState)
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: MacroEngineBase{macroState},
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syncpoints{state.soc->host1x.syncpoints},
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@ -76,6 +117,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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__attribute__((always_inline)) void Maxwell3D::FlushDeferredDraw() {
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if (batchEnableState.drawActive) {
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batchEnableState.drawActive = false;
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if (CheckRenderEnable())
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interconnect.Draw(deferredDraw.drawTopology, *registers.streamOutputEnable, deferredDraw.indexed, deferredDraw.drawCount, deferredDraw.drawFirst, deferredDraw.instanceCount, deferredDraw.drawBaseVertex, deferredDraw.drawBaseInstance);
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deferredDraw.instanceCount = 1;
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}
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@ -229,6 +271,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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})
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ENGINE_CASE(clearSurface, {
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if (CheckRenderEnable())
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interconnect.Clear(clearSurface);
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})
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@ -489,22 +532,22 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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auto topology{static_cast<type::DrawTopology>(drawTopology)};
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registers.globalBaseInstanceIndex = globalBaseInstanceIndex;
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registers.vertexArrayStart = vertexArrayStart;
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if (CheckRenderEnable())
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interconnect.Draw(topology, *registers.streamOutputEnable, false, vertexArrayCount, vertexArrayStart, instanceCount, 0, globalBaseInstanceIndex);
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registers.globalBaseInstanceIndex = 0;
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}
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void Maxwell3D::DrawIndexedInstanced(u32 drawTopology, u32 indexBufferCount, u32 instanceCount, u32 globalBaseVertexIndex, u32 indexBufferFirst, u32 globalBaseInstanceIndex) {
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FlushEngineState();
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auto topology{static_cast<type::DrawTopology>(drawTopology)};
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if (CheckRenderEnable())
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interconnect.Draw(topology, *registers.streamOutputEnable, true, indexBufferCount, indexBufferFirst, instanceCount, globalBaseVertexIndex, globalBaseInstanceIndex);
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}
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void Maxwell3D::DrawIndexedIndirect(u32 drawTopology, span<u8> indirectBuffer, u32 count, u32 stride) {
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FlushEngineState();
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auto topology{static_cast<type::DrawTopology>(drawTopology)};
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if (CheckRenderEnable())
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interconnect.DrawIndirect(topology, *registers.streamOutputEnable, true, indirectBuffer, count, stride);
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}
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@ -69,6 +69,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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}
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} deferredDraw{};
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bool CheckRenderEnable();
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type::DrawTopology ApplyTopologyOverride(type::DrawTopology beginMethodTopology);
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void FlushDeferredDraw();
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@ -268,6 +270,19 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x54F, type::MultisampleControl> multisampleControl;
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struct RenderEnable {
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enum class Mode : u32 {
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False = 0,
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True = 1,
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Conditional = 2,
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RenderIfEqual = 3,
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RenderIfNotEqual = 4,
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};
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Address offset;
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Mode mode;
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};
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Register<0x554, RenderEnable> renderEnable;
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Register<0x557, TexSamplerPool> texSamplerPool;
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Register<0x55B, float> slopeScaleDepthBias;
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@ -375,6 +390,19 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x64B, u32> viewportScaleOffsetEnable;
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Register<0x64F, type::ViewportClipControl> viewportClipControl;
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struct RenderEnableOverride {
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enum class Mode : u8 {
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UseRenderEnable = 0,
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AlwaysRender = 1,
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NeverRender = 2,
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};
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Mode mode : 2;
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u32 _pad_ : 30;
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};
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Register<0x651, RenderEnableOverride> renderEnableOverride;
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Register<0x652, type::PrimitiveTopologyControl> primitiveTopologyControl;
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Register<0x65C, type::PrimitiveTopology> primitiveTopology;
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