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Implement B8G8R8A8{Unorm/Srgb}
RT Format
Needed by Maxwell3D Register Initialization
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@ -101,6 +101,10 @@ namespace skyline::gpu::interconnect {
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return format::R16G16B16A16Uint;
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case maxwell3d::RenderTarget::ColorFormat::R16G16B16A16Float:
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return format::R16G16B16A16Float;
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case maxwell3d::RenderTarget::ColorFormat::B8G8R8A8Unorm:
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return format::B8G8R8A8Unorm;
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case maxwell3d::RenderTarget::ColorFormat::B8G8R8A8Srgb:
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return format::B8G8R8A8Srgb;
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case maxwell3d::RenderTarget::ColorFormat::A2B10G10R10Unorm:
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return format::A2B10G10R10Unorm;
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case maxwell3d::RenderTarget::ColorFormat::R8G8B8A8Unorm:
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@ -40,6 +40,6 @@ namespace skyline::gpu::format {
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constexpr Format R16G16B16A16Sint{sizeof(u16) * 4, vkf::eR16G16B16A16Sint};
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constexpr Format R16G16B16A16Uint{sizeof(u16) * 4, vkf::eR16G16B16A16Uint};
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constexpr Format R16G16B16A16Float{sizeof(u16) * 4, vkf::eR16G16B16A16Sfloat};
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/**
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constexpr Format B8G8R8A8Unorm{sizeof(u32), vkf::eB8G8R8A8Unorm};
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constexpr Format B8G8R8A8Srgb{sizeof(u32), vkf::eB8G8R8A8Srgb};
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}
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@ -58,6 +58,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
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R16G16B16A16Sint = 0xC8,
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R16G16B16A16Uint = 0xC9,
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R16G16B16A16Float = 0xCA,
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B8G8R8A8Unorm = 0xCF,
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B8G8R8A8Srgb = 0xD0,
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A2B10G10R10Unorm = 0xD1,
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R8G8B8A8Unorm = 0xD5,
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A8B8G8R8Srgb = 0xD6,
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