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Introduce reworked Maxwell 3D core interconnect
This mainly distributes operations down to activeState and pipelineState, aside from clears which are implemented in-place. The exposed interface is much reduced as opposed to the previous GraphicsContext system due to the newly introduced dirty system, this should hopefully make the code more maintainable and keep actual rendering operations seperate from primitive restart state or whatever. Currently draws are unimplemented and the only full implemented things are clears and constant buffer operations.
This commit is contained in:
Billy Laws
parent
37b821a4dc
commit
ef11900a39
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/Ryujinx/)
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <gpu/interconnect/command_executor.h>
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#include <vulkan/vulkan_structs.hpp>
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#include "common/utils.h"
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#include "maxwell_3d.h"
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#include "common.h"
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#include "pipeline_state.h"
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#include "services/hosbinder/GraphicBufferProducer.h"
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namespace skyline::gpu::interconnect::maxwell3d {
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Maxwell3D::Maxwell3D(GPU &gpu,
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soc::gm20b::ChannelContext &channelCtx,
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gpu::interconnect::CommandExecutor &executor,
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DirtyManager &manager,
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const EngineRegisterBundle ®isterBundle)
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: ctx{channelCtx, executor, gpu},
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activeState{manager, registerBundle.activeStateRegisters},
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clearEngineRegisters{registerBundle.clearRegisters},
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constantBuffers{manager, registerBundle.constantBufferSelectorRegisters},
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directState{activeState.directState} {
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executor.AddFlushCallback([this] {
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activeState.MarkAllDirty();
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constantBuffers.MarkAllDirty();
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});
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}
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vk::Rect2D Maxwell3D::GetClearScissor() {
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const auto &clearSurfaceControl{clearEngineRegisters.clearSurfaceControl};
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const auto &surfaceClip{clearEngineRegisters.surfaceClip};
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vk::Rect2D scissor{
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{surfaceClip.horizontal.x, surfaceClip.vertical.y},
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{surfaceClip.horizontal.width, surfaceClip.vertical.height}
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};
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auto rectIntersection{[](const vk::Rect2D &a, const vk::Rect2D &b) -> vk::Rect2D {
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vk::Offset2D maxOffset{std::max(a.offset.x, b.offset.x), std::max(a.offset.y, b.offset.y)};
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i32 signedWidth{std::min(a.offset.x + static_cast<i32>(a.extent.width), b.offset.x + static_cast<i32>(b.extent.width)) - maxOffset.x};
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i32 signedHeight{std::min(a.offset.y + static_cast<i32>(a.extent.height), b.offset.y + static_cast<i32>(b.extent.height)) - maxOffset.y};
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return {
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maxOffset,
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{static_cast<u32>(std::max(signedWidth, 0)),
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static_cast<u32>(std::max(signedHeight, 0))}
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};
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}};
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if (clearSurfaceControl.useClearRect) {
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const auto &clearRect{clearEngineRegisters.clearRect};
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scissor = rectIntersection(scissor, {
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{clearRect.horizontal.xMin, clearRect.vertical.yMin},
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{static_cast<u32>(clearRect.horizontal.xMax - clearRect.horizontal.xMin), static_cast<u32>(clearRect.vertical.yMax - clearRect.vertical.yMin)}
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});
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}
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if (clearSurfaceControl.useScissor0) {
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const auto &scissor0{clearEngineRegisters.scissor0};
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scissor = rectIntersection(scissor, {
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{scissor0.horizontal.xMin, scissor0.vertical.yMin},
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{static_cast<u32>(scissor0.horizontal.xMax - scissor0.horizontal.xMin), static_cast<u32>(scissor0.vertical.yMax - scissor0.vertical.yMin)}
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});
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}
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if (clearSurfaceControl.useViewportClip0) {
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const auto &viewportClip0{clearEngineRegisters.viewportClip0};
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scissor = rectIntersection(scissor, {
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{viewportClip0.horizontal.x0, viewportClip0.vertical.y0},
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{viewportClip0.horizontal.width, viewportClip0.vertical.height}
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});
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}
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return scissor;
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}
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void Maxwell3D::LoadConstantBuffer(span<u32> data, u32 offset) {
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constantBuffers.Load(ctx, data, offset);
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}
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void Maxwell3D::BindConstantBuffer(engine::PipelineStage stage, u32 index, bool enable) {
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if (enable)
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constantBuffers.Bind(ctx, stage, index);
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else
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constantBuffers.Unbind(stage, index);
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}
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void Maxwell3D::Clear(engine::ClearSurface &clearSurface) {
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auto scissor{GetClearScissor()};
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if (scissor.extent.width == 0 || scissor.extent.height == 0)
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return;
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auto needsAttachmentClearCmd{[&](auto &view) {
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return scissor.offset.x != 0 || scissor.offset.y != 0 ||
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scissor.extent != vk::Extent2D{view->texture->dimensions} ||
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view->range.layerCount != 1 || view->range.baseArrayLayer != 0 || clearSurface.rtArrayIndex != 0;
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}};
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auto clearRects{util::MakeFilledArray<vk::ClearRect, 2>(vk::ClearRect{.rect = scissor, .baseArrayLayer = clearSurface.rtArrayIndex, .layerCount = 1})};
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boost::container::small_vector<vk::ClearAttachment, 2> clearAttachments;
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std::shared_ptr<TextureView> colorView{};
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std::shared_ptr<TextureView> depthStencilView{};
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if (clearSurface.rEnable || clearSurface.gEnable || clearSurface.bEnable || clearSurface.aEnable) {
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colorView = activeState.GetColorRenderTargetForClear(ctx, clearSurface.mrtSelect);
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ctx.executor.AttachTexture(&*colorView);
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if (!(clearSurface.rEnable && clearSurface.gEnable && clearSurface.bEnable && clearSurface.aEnable))
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Logger::Warn("Partial clears are unimplemented! Performing full clear instead");
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if (!(colorView->range.aspectMask & vk::ImageAspectFlagBits::eColor)) {
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Logger::Warn("Colour RT used in clear lacks colour aspect"); // TODO: Drop this check after texman rework
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return;
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}
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if (needsAttachmentClearCmd(colorView)) {
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clearAttachments.push_back({ .aspectMask = colorView->range.aspectMask, .clearValue = {clearEngineRegisters.colorClearValue} });
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} else {
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ctx.executor.AddClearColorSubpass(&*colorView, clearEngineRegisters.colorClearValue);
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colorView = {}; // Will avoid adding as colour RT
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}
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}
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if (clearSurface.stencilEnable || clearSurface.zEnable) {
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depthStencilView = activeState.GetDepthRenderTargetForClear(ctx);
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ctx.executor.AttachTexture(&*depthStencilView);
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bool viewHasDepth{depthStencilView->range.aspectMask & vk::ImageAspectFlagBits::eDepth}, viewHasStencil{depthStencilView->range.aspectMask & vk::ImageAspectFlagBits::eStencil};
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vk::ClearDepthStencilValue clearValue{
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.depth = clearEngineRegisters.depthClearValue,
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.stencil = clearEngineRegisters.stencilClearValue
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};
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if (!viewHasDepth && !viewHasStencil) {
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Logger::Warn("Depth stencil RT used in clear lacks depth or stencil aspects"); // TODO: Drop this check after texman rework
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return;
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}
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if (needsAttachmentClearCmd(depthStencilView) || (!clearSurface.stencilEnable && viewHasStencil) || (!clearSurface.zEnable && viewHasDepth )) { // Subpass clears write to all aspects of the texture, so we can't use them when only one component is enabled
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clearAttachments.push_back({ .aspectMask = depthStencilView->range.aspectMask, .clearValue = clearValue });
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} else {
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ctx.executor.AddClearDepthStencilSubpass(&*depthStencilView, clearValue);
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depthStencilView = {}; // Will avoid adding as depth-stencil RT
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}
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}
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// Always use surfaceClip for render area since it's more likely to match the renderArea of draws and avoid an RP break
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const auto &surfaceClip{clearEngineRegisters.surfaceClip};
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vk::Rect2D renderArea{{surfaceClip.horizontal.x, surfaceClip.vertical.y}, {surfaceClip.horizontal.width, surfaceClip.vertical.height}};
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std::array<TextureView *, 1> colorAttachments{colorView ? &*colorView : nullptr};
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ctx.executor.AddSubpass([clearAttachments, clearRects](vk::raii::CommandBuffer &commandBuffer, const std::shared_ptr<FenceCycle> &, GPU &, vk::RenderPass, u32) {
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commandBuffer.clearAttachments(clearAttachments, span(clearRects).first(clearAttachments.size()));
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}, renderArea, {}, colorView ? colorAttachments : span<TextureView *>{}, depthStencilView ? &*depthStencilView : nullptr);
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}
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void Maxwell3D::Draw(engine::DrawTopology topology, bool indexed, u32 count, u32 first, u32 instanceCount, u32 vertexOffset, u32 firstInstance) {
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StateUpdateBuilder builder{};
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activeState.Update(ctx, builder, indexed, topology, count);
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}
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}
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@ -0,0 +1,67 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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#include "common.h"
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#include "active_state.h"
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#include "constant_buffers.h"
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namespace skyline::gpu::interconnect::maxwell3d {
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/**
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* @brief The core Maxwell 3D interconnect object, directly accessed by the engine code to perform rendering operations
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*/
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class Maxwell3D {
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public:
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struct ClearEngineRegisters {
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const engine::Scissor &scissor0;
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const engine::ViewportClip &viewportClip0;
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const engine::ClearRect &clearRect;
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const std::array<u32, 4> &colorClearValue;
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const float &depthClearValue;
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const u32 &stencilClearValue;
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const engine::SurfaceClip &surfaceClip;
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const engine::ClearSurfaceControl &clearSurfaceControl;
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};
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/**
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* @brief The full set of register state used by the GPU interconnect
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*/
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struct EngineRegisterBundle {
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ActiveState::EngineRegisters activeStateRegisters;
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ClearEngineRegisters clearRegisters;
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ConstantBufferSelectorState::EngineRegisters constantBufferSelectorRegisters;
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};
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private:
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InterconnectContext ctx;
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ActiveState activeState;
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ClearEngineRegisters clearEngineRegisters;
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ConstantBuffers constantBuffers;
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vk::Rect2D GetClearScissor();
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public:
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DirectPipelineState &directState;
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Maxwell3D(GPU &gpu,
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soc::gm20b::ChannelContext &channelCtx,
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gpu::interconnect::CommandExecutor &executor,
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DirtyManager &manager,
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const EngineRegisterBundle ®isterBundle);
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/**
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* @brief Loads the given data into the constant buffer pointed by the constant buffer selector starting at the given offset
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*/
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void LoadConstantBuffer(span<u32> data, u32 offset);
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/**
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* @brief Binds the constant buffer selector to the given pipeline stage
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*/
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void BindConstantBuffer(engine::PipelineStage stage, u32 index, bool enable);
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void Clear(engine::ClearSurface &clearSurface);
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void Draw(engine::DrawTopology topology, bool indexed, u32 count, u32 first, u32 instanceCount, u32 vertexOffset, u32 firstInstance);
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};
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}
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