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Don't populate colour targets with an empty write mask
Avoids breaking VK spec in BOTW, as it has the same colour attachment bound twice, but the former is masked out entirely.
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commit
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@ -300,6 +300,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
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void ColorBlendState::Flush(PackedPipelineState &packedState) {
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packedState.logicOpEnable = engine->logicOp.enable;
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packedState.SetLogicOp(engine->logicOp.func);
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writtenCtMask.reset();
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for (u32 i{}; i < engine::ColorTargetCount; i++) {
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auto ctWrite{[&]() {
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@ -315,6 +316,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
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packedState.SetAttachmentBlendState(i, enable, ctWrite, engine->blendPerTargets[i]);
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else
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packedState.SetAttachmentBlendState(i, enable, ctWrite, engine->blend);
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writtenCtMask.set(i, ctWrite.Any());
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}
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}
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@ -392,10 +395,12 @@ namespace skyline::gpu::interconnect::maxwell3d {
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shaderBinaries[i] = stage.binary;
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}
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colorBlend.Update(packedState);
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colorAttachments.clear();
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packedState.colorRenderTargetFormats = {};
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for (size_t i{}; i < engine::ColorTargetCount; i++) {
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if (i < ctSelect.count) {
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if (i < ctSelect.count && colorBlend.Get().writtenCtMask.test(i)) {
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const auto &rt{colorRenderTargets[ctSelect[i]].UpdateGet(ctx, packedState)};
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const auto view{rt.view.get()};
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packedState.SetColorRenderTargetFormat(ctSelect[i], rt.format);
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@ -417,7 +422,6 @@ namespace skyline::gpu::interconnect::maxwell3d {
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tessellation.Update(packedState);
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rasterization.Update(packedState);
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depthStencil.Update(packedState);
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colorBlend.Update(packedState);
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transformFeedback.Update(packedState);
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globalShaderConfig.Update(packedState);
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@ -234,6 +234,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
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dirty::BoundSubresource<EngineRegisters> engine;
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public:
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std::bitset<engine::ColorTargetCount> writtenCtMask{};
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ColorBlendState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine);
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void Flush(PackedPipelineState &packedState);
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@ -718,6 +718,10 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
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static_assert(sizeof(ViewportClipControl) == sizeof(u32));
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union CtWrite {
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bool Any() const {
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return rEnable || gEnable || bEnable || aEnable;
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}
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u32 raw;
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struct {
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