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https://github.com/skyline-emu/skyline.git
synced 2024-12-27 16:45:30 +03:00
Fix system register state handling
We failed to preserve NCSZ, and and we stored instead of loaded FPCR when returning to guest.
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@ -141,6 +141,7 @@ namespace skyline::kernel::type {
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"MOV X29, XZR\n\t"
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"MOV X29, XZR\n\t"
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"MSR FPSR, XZR\n\t"
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"MSR FPSR, XZR\n\t"
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"MSR FPCR, XZR\n\t"
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"MSR FPCR, XZR\n\t"
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"MSR NZCV, XZR\n\t"
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"DUP V0.16B, WZR\n\t"
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"DUP V0.16B, WZR\n\t"
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"DUP V1.16B, WZR\n\t"
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"DUP V1.16B, WZR\n\t"
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"DUP V2.16B, WZR\n\t"
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"DUP V2.16B, WZR\n\t"
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@ -38,11 +38,16 @@ SaveCtx:
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STP Q28, Q29, [LR, #(0xA0 + 16 * 28)]
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STP Q28, Q29, [LR, #(0xA0 + 16 * 28)]
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STP Q30, Q31, [LR, #(0xA0 + 16 * 30)]
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STP Q30, Q31, [LR, #(0xA0 + 16 * 30)]
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/* Store FPCR/FPSR */
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/* Store System Registers */
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STR X0, [SP, #-16]!
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MRS X0, FPSR
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MRS X0, FPSR
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STR W0, [LR, #0x298]
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STR W0, [LR, #0x298]
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MRS X1, FPCR
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MRS X0, FPCR
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STR W1, [LR, #0x29C]
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STR W0, [LR, #0x29C]
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MRS X0, NZCV
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STR W0, [LR, #0x2C0]
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LDR X0, [SP], #16
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/* Restore Scratch Register */
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/* Restore Scratch Register */
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LDR LR, [SP, #8]
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LDR LR, [SP, #8]
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@ -72,11 +77,13 @@ LoadCtx:
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LDP Q28, Q29, [LR, #(0xA0 + 16 * 28)]
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LDP Q28, Q29, [LR, #(0xA0 + 16 * 28)]
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LDP Q30, Q31, [LR, #(0xA0 + 16 * 30)]
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LDP Q30, Q31, [LR, #(0xA0 + 16 * 30)]
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/* Store FPCR/FPSR */
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/* Load System Registers */
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MRS X0, FPSR
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LDR W0, [LR, #0x298]
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STR W0, [LR, #0x298]
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MSR FPSR, X0
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MRS X1, FPCR
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LDR W0, [LR, #0x29C]
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STR W1, [LR, #0x29C]
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MSR FPCR, X0
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LDR W0, [LR, #0x2C0]
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MSR NZCV, X0
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/* Load GP Registers */
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/* Load GP Registers */
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LDP X0, X1, [LR, #(8 * 0)]
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LDP X0, X1, [LR, #(8 * 0)]
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@ -98,13 +98,14 @@ namespace skyline {
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u8 *hostSp; //!< Host Stack Pointer, same as above
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u8 *hostSp; //!< Host Stack Pointer, same as above
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u8 *tpidrroEl0; //!< Emulated HOS TPIDRRO_EL0
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u8 *tpidrroEl0; //!< Emulated HOS TPIDRRO_EL0
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u8 *tpidrEl0; //!< Emulated HOS TPIDR_EL0
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u8 *tpidrEl0; //!< Emulated HOS TPIDR_EL0
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u32 nzcv;
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const DeviceState *state;
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const DeviceState *state;
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u64 magic{constant::SkyTlsMagic};
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u64 magic{constant::SkyTlsMagic};
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};
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};
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namespace guest {
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namespace guest {
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constexpr size_t SaveCtxSize{34}; //!< The size of the SaveCtx function in 32-bit ARMv8 instructions
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constexpr size_t SaveCtxSize{38}; //!< The size of the SaveCtx function in 32-bit ARMv8 instructions
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constexpr size_t LoadCtxSize{34}; //!< The size of the LoadCtx function in 32-bit ARMv8 instructions
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constexpr size_t LoadCtxSize{36}; //!< The size of the LoadCtx function in 32-bit ARMv8 instructions
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/**
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/**
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* @brief Saves the context from CPU registers into TLS
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* @brief Saves the context from CPU registers into TLS
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