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Implement Blocklinear TIC Type
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723189a948
commit
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@ -1772,17 +1772,21 @@ namespace skyline::gpu::interconnect {
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size_t size; //!< The size of the texture in bytes
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size_t size; //!< The size of the texture in bytes
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if (textureControl.headerType == TextureImageControl::HeaderType::Pitch) {
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if (textureControl.headerType == TextureImageControl::HeaderType::Pitch) {
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u32 pitch{static_cast<u32>(textureControl.tileConfig.pitchHigh) << TextureImageControl::TileConfig::PitchAlignmentBits};
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guest.tileConfig = {
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guest.tileConfig = {
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.mode = texture::TileMode::Pitch,
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.mode = texture::TileMode::Pitch,
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.pitch = pitch,
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.pitch = static_cast<u32>(textureControl.tileConfig.pitchHigh) << TextureImageControl::TileConfig::PitchAlignmentBits,
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};
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} else if (textureControl.headerType == TextureImageControl::HeaderType::BlockLinear) {
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guest.tileConfig = {
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.mode = texture::TileMode::Block,
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.blockHeight = static_cast<u8>(1U << textureControl.tileConfig.tileHeightGobsLog2),
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.blockDepth = static_cast<u8>(1U << textureControl.tileConfig.tileDepthGobsLog2),
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};
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};
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size = pitch * guest.dimensions.height * guest.dimensions.depth * guest.layerCount;
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} else {
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} else {
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throw exception("Unsupported TIC Header Type: {}", static_cast<u32>(textureControl.headerType));
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throw exception("Unsupported TIC Header Type: {}", static_cast<u32>(textureControl.headerType));
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}
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}
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auto mappings{channelCtx.asCtx->gmmu.TranslateRange(textureControl.Iova(), size)};
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auto mappings{channelCtx.asCtx->gmmu.TranslateRange(textureControl.Iova(), guest.GetLayerSize() * (guest.layerCount - guest.baseArrayLayer))};
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guest.mappings.assign(mappings.begin(), mappings.end());
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guest.mappings.assign(mappings.begin(), mappings.end());
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} else if (auto textureView{poolTexture.view.lock()}; textureView != nullptr) {
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} else if (auto textureView{poolTexture.view.lock()}; textureView != nullptr) {
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// If the entry already exists and the view is still valid then we return it directly
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// If the entry already exists and the view is still valid then we return it directly
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